The disclosure relates generally to a method and apparatus for designing an integrated circuit, and more particularly, to a method and apparatus for designing an integrated circuit to operate at a desired clock frequency range.
Timing analysis and optimization is a design process by which an integrated circuit design is characterized and modified to meet its timing requirement in order to assure the fabricated integrated circuit will operate at the desired clock frequency range. However, the scaling down of fabrication process technologies has increased the process variation that impacts the frequency performance of integrated circuits by reducing the timing yield, which implies the number of integrated circuits that achieve the target frequency out of the total number of integrated circuits produced.
For example, in high-performance microprocessor designs, excessive design margins caused by the increased process variation make it difficult to achieve the target frequency performance consistently all parts. In order to solve the problem, after a batch of microprocessor chips has been fabricated, the frequency selection process is needed to sort the chips into several ranks according to the measured maximum frequencies. In application specific integrated circuit (ASIC) designs, sufficient margins for process variation are required to achieve the target frequency at the expected yield. Compared with high-performance microprocessor designs, ASIC designs tend to overestimate the process variation at the circuit design phase by enlarging the design margins in its timing analysis stage to absorb all possible process variations in order to assure that the fabricated integrated circuit will operate at its desired clock frequency range. In other words, timing analysis in ASIC designs is conservative and considers the design margins pessimistically. For example, known timing related methods in ASIC designs include closing performance at the worst performance corner; using the worst possible uncertainties to account for on-chip-variation (OCV); and applying the worst case IR drop and worst case interconnects conditions. The overestimation by piling up so much pessimism at the same time, however, has an adverse effect on area and power in ASIC designs. The overestimation may cause timing goals to be missed or become excessively tight during timing analysis so that the designers have to tune a design iteratively to achieve the target frequency performance, which increases the design turnaround time. Additionally, the overestimation introduces excessive power consumption due to the pessimistic guard-bands. That is, the known conservative methods are too pessimistic to result in competitive products.
Statistical static timing analysis (SSTA), which analyzes circuit delays statistically by replacing deterministic delay with statistical distribution, is a known method for solving the above issues. The main concept of SSTA is to statistically consider the random variation of OCV in timing analysis by replacing the normal deterministic timing of gates and interconnects with probability distributions, thereby finding the most possible performance critical corner for timing analysis. However, SSTA is a very complex and time consuming analytical method, especially with realistic (non-Gaussian) distributions. Further, SSTA considers each timing critical path independently and neglects the timing correlation between adjacent timing critical paths in adjacent clock cycles. Moreover, it is difficult to couple SSTA to a timing optimization or algorithm in a standard ASIC design flow because it does not provide the data the algorithm needs. In other words, SSTA outputs a distribution of possible circuit outcomes, which is difficult for use in timing optimization.
Accordingly, there exists a need for other method and apparatus for designing an integrated circuit to operate at a desired clock frequency range in order to address one or more of the above-noted drawbacks.